1. Field of the Invention
The present invention is directed to a semiconductor device and to a method of manufacturing an MOS or MIS-type semiconductor device.
2. Description of the Prior Art
As semiconductor devices have hitherto been constructed to have a hyperfine structure and a high degree of integration, the configuration of MOS transistors also has become hyperfine. The minuteness of element dimensions, however, causes the problem that properties associated with hot carriers tend to be deteriorated. In order to obviate this problem, there was proposed an LDD (Lightly Doped Drain) structure. An improvement of the LDD structure is described on pages 38-41 of "The Impact of Gate-Drain Overlapped LDD (Gold) for Deep Submicron VLSI's", IEDM Tech. Dig., written by R. Izawa, T. Kure and E. Takeda, published in 1987.
A manufacturing method reported in this document will hereinafter be described with reference to FIGS. 2 which show the following components: a p-type semiconductor substrate 201; a gate oxide film 202; a polysilicon film 203; a natural oxide film 204; a polysilicon film 205; a silicon oxide film 206; an n-type impurity layer 207 having a low concentration; a side wall 208 of an oxide film; an n-type impurity layer 209 having a high concentration; and an oxide film 210.
To start with, the p-type semiconductor substrate 201 undergoes thermal oxidation of form the gate oxide film 202. Next, the polysilicon film 203 is deposited to a small thickness by the CVD method which is thereafter left exposed to the air, thus forming the natural oxide film 204 having a thickness of 5 to 101/8. Subsequently, the polysilicon film 205 and the silicon oxide film 206 are sequentially deposited by the CVD method. As illustrated in FIG. 2(a), unnecessary portions of the silicon oxide film 206 are eliminated by photoetching. Dry etching is, as depicted in FIG. 2(b), effected, with the oxide film 206 serving as a mask, to remove unnecessary portions of the polysilicon film 205. The n-type impurity layer 207 is formed by performing ion implantation of an n-type impurity, i.e., phosphorus, using silicon oxide film 206 and polysilicon film 205 as a mask. In the wake of this process, as illustrated in FIG. 2(c), the side wall insulating film 208, conceived as a silicon oxide film, is formed by dry etching after depositing a silicon oxide film by the CVD method. Oxidation is, as depicted in FIG. 2(d), carried out at 800.degree. in a wet atmosphere, thus forming the oxide film 210. Subsequently, the n-type impurity layer 209 is formed by effecting ion implantation of an n-type impurity, viz., arsenic, wherein the gate electrode 203, oxide film 206 and side wall insulating film 208 serve as a mask.
There arise, however, the following problems inherent in the above-mentioned prior art process. Although properties of the MOS transistor largely vary depending on the lateral length of the oxide film 210, it is difficult to control the dimensions of that film because the lateral length is determined by the thickness of the polycrystalline silicon film 203 and by oxidizing conditions in the wet atmosphere. Especially when the gate length of the MOS transistor is as minute as the submicron region, there are caused substantial fluctuations in the transistor properties due to variations in the lateral length of the oxide film 210.
Based on the prior art process, when depositing the silicon oxide film 208 by the CVD method, the oxide film 206 on the gate electrodes 203 and 205 overhangs, and hence, as illustrated in FIG. 3, it is hard for oxide film 208 to form under film 206, resulting in formation of voids 311. This leads to a deterioration of the moisture resistance property of the MOS transistor.
The prior art described above presents additional problems. When forming the MOS transistor, the thicknesses of the films disposed on a channel--i.e., the gate oxide film 202, polysilicon film 203, natural oxide film 204, polysilicon film 205 and silicon oxide film 206--combine to provide a large step. Consequently, a metallization layer is further formed on the gate electrode so as to traverse this layer. In this state, the metallization layer on the gate electrode is in some cases disconnected due to the above-mentioned step, or, alternatively, the metallization layer is short-circuited because of the portions which remain unetched when forming the metallization layer on the gate electrode.